Four major documents at hand:
1. Programming Introduction (78 pages)
2. Hardware Reference (210 pages)
2.1 CPX core (426 pages)
2.2 Hearing Accelerator Core (354 pages)
The system is designed by ON semiconductor, which is built up in 1999.
Doc 1: Programming Introduction
Chapter 1: Introduction Chapter 2 Architecture Overview Chapter 3 Design Information
Chapter 4: Sample code Chapter 5: Porting Guide
Doc 2: Hardware Reference
Chapter 1: Introduction Chapter 2: System Overview Chapter 3: CFX core
Chapter 4: Hear Core Chapter 5: Memory Chapter 6: Fifo controller
Chapter 7: Input/Output Controller Chapter 8: Input stage Chapter 9: Output Stage
Chapter 10: PCM & IIS interface Chapter 11: Peripherials Chapter 12: External Interfaces
Chapter 13: Clock Components Chapter 14: Power Components
Addix: registers, sampling frequency
Doc 2.1 CFX core
Chapter 1: Introduction Chapter 2: CFX architecture overview Chapter 3: Instruction type
Chapter 4: Data Computation Units Chapter 5: Data movement Units Chapter 6: Address Generator
Chapter 7: Program Control Units Chapter 8: Memory spaces Chapter 9: Processing Modes
Chapter 10: CPX instructin Set
Addix: Instruction Set Summary Opcode Map
Doc 2.2 Hear core
Chapter 1: Introduction Chapter 2: Usage Model Chapter 3: Modules
Chapter 4: Moduel Reference Chapter 5: Hear Configuration Tool
Addix: optimized WOLF windows
Now start to go through doc 1, Chapter 1.
Board Name: Ezairo 5900
CFX: 2 MAC 24bit DSP Coare
Hear core
FIFO
130nm technology
CRC generator & security module & RF interface
doc 1, chapter 2 (8 pages)
CFX core:
Task1: configure the system
Task2: coordinate the flow of signal data progressing through the system
Task3: do some signal processing applications that cannot be handled by Hear core.
CFX core features:
1. harvard structure, seperate progrm memory and two data memories with seperate buses.
2. can access to the Hear core memories.
3. Both ROM and RAM for program to store user's applications and interrupt vector. use as instruction memory if through the instruction memory bus. use as data for cfx core if through P memory bus.
4. P bus can be used to access Hear core microcode memory
5. Two sepearate data memories: 24bit X and 24bit Y. or 48bit XY.
6. X bus can also access Hear core memories and registers.
Hear core features:
1. 24bit signal processing engine.
2. FIR/IIR, vector based arithmetic operation, WOLA filterbank, FFT etc.
3. Block Floating Point (BFP): avoid overflow
4. Hear core supports 24 different function chains: 16 from CFX, 8 from interrupt triggered by FIFO controller
Shared Memory:
1. 48 bit width
2. can be accessed by CFX via P bus and X bus.
3. H0, H1, H2, H3,H4, H5: general memory for filter bank etc. 128x48bit
4. A & B for FIFO controller 1024x24bit
5. C & D for microcode modules 1024x24bit
6. Hear can access data 96bit a time for special algorithms.
FIFO controller:
1. for circular buffer
2. resolve access conflict of the two cores via shared memory bus
3. it tracks incoming data and output data. trigger funciton chain of Hear core and interrupt of CFX core.
IO controller:
1. any combination of 4 analog input channels (in input stage) and two pcm channels
2. output to direct digital output or 2 pcm channels.
Firmware components:
1. accessible using ON semiconductor SignaKlara IDE, containing:
a. system included files and macros
b. system library
c. math library
d. eeprom library
e. file system
f. program ROM
g. bootloader
Doc 1, chapter 3(8 pages)
Orela 4500 Ezairo 5900
RCore CFX core
Wola filter Hearing core
load balance on two cores is important to power efficiency.
partition algorithms
fixed size, try to balance noise and power-consuming
data flow:
Orela 4500: input stage --> input fifo --> Rcore --> ouptut fifo --> output stage
Ezairo 5900: much more complex IOC and FIFO Controller, perfect for adptive feedback canceller.
Doc 1, chapter 4 (10 pages)
sample code as template, for learn purpose, not most efficient or optimal way
