Starkey Lab Project ( continued from Oct 3, 10)

Current Project:  Denver ( two series: Opal RIC 312 with RF & Power 13 BTE)
New Project:  Evanston (two series: Ezairo Only wireless & Ezaino +E2M2)
E2M2 with a V8 uP which is majorly deal with wireless communication with wireless Receiver/Transfer chip.

Doc 2:  Hardware Reference (210 pages)

Chapter 1: Introduction (3 pages)
pre-requirement:  assembly level programming + dsp application + audio systems + dsp tools.

Chapter 2: System Overview (6 pages)
CFX core:  data flow control  + dsp applications
Hear core:  help CFX to do dsp applications, such as WOLA, FFT etc.
IOC:   together with FIFO, provide data input and output to and from CFX core and Hear core.
CPX local memory:  Program Memory + X data memory + Y data memory
Hear local memory:   Microcode memory
Shared memory:  can be accessed by Hear core and CFX core.

Hear core:
Microcode modules --> function chains --> triggered by CFX commands or events from FIFO
Floating point block:  for large dynamic range data such as subband

Hear core shared memory:  for tempory data, algorithm coefficients, signal data.

FIFO:
1.  for circular buffer
2.  access conflict from the two cores
3.  track data input and output, trigger function chains. etc.

Peripherial:
1. an interrupt controller
2. two general purpose timers
3. a watch-dog timer
4. crc
5. security block

Interfaces:
1. IIC debug interface
2. IIC general purpose interface
3. SPI interface
4. UART interface
5. 5 LSAD inputs
6. 5 GPIO pads

IOC:
1. 4 input channels multiplexed from 5 analog input
2. 1 output channel to drive receiver

IIS and PCM interface:
1. communicate with iis device
2. communicate with pcm device
3. communicate with NOAHlink device

Clock:
1. one on-chip oscillator: 5.12M
2. one standby oscillator
3. allow for selection other clock source
4. series of clock divider

Chapter 3: CFX core (4 pages)
1. Processor Overview
CFX core:  dual Harvard, duaol MAC architecture, 24bit
BootROM on it to initialize applications
Debug controller, memory mapped registers
2. Application Overview
Tasks run on CFX core: 
          Configure IOC and input stage/IIS or PCM to get input
          Configure IOC and output stage/IIS or PCM to distribute output signal
          Configure FIFO to handle input, output and immediate data
          Configure the HEAR core
           Execute DSP algorithms
           Support Debug

Chapter 4: Hear core (10 pages)
1. Overview
not programmable, no direct debug access,
2. Function Chain Controller
3. Block Floating-Point