Starkey Lab Project (continued with Oct. 6, 10)

Doc 2, Chapter 4  Hear Core

Microcode Module --> linked up --> Function Chains

System_control_register (D_System_Ctrl):   Hear_pause bit,  Hear_resume bit,  Hear_running bit, Hear_Rest bit

Function_chain_control_reg (D_Hear_FC_Enable)
D_Hear_CMD_0_7   & D_Hear_CMD_8_15
D_Hear_FC_Priority:    Normal & High   High Priority Funciton chains are handled first
              if the same priority level, CFX command first, then FIFO A interrupt, then FIFO B interrupt
              24 funcitons trigger accepted:  16 from CFX commands, 8 from FIFO A&B interrupt
D_Hear_FC_Status:   pending or not

Blcok_Floating_Point_reg (D_HEAR_BFP):

Chapter 5  Memory (16 pages)
all memories are signle port.
program memory & data memory
memory attached to CFX & memory attached to Hear core
all memory attached to Hear core can be accessed by CFX by P bus or X bus
Write-back-buffers:   allow the sytem to read back the value written to the memory address in the previous cycle without stalling the instruction pipeline.
Interrupt Vector:
system-rest, watchdog, timer1, timer2, spi, iic, shared iis and pcm, gpio, hear event 0~7, Fifo A0~3, B0~3,
UART Receive, UART Transmit

Chapter 6  FIFO Controller ( 10 Pages)
FIFO A 0 , 1, 2, 3
FIFO B 0, 1, 2, 3
Each FIFO -- seperate control registers --> map to X memory space --> 24bit
                            START
                            END
                            SIZE
                            Enable: note: enalbe register is P memory space
FIFO buffers for:  block input, block output, application
FIFO_PTR and FIFO_Count
IOBLOCK_PTR and BASE_PTR and BLOCK_SIZE and BLOCK_CNT
FIFO access priority is fixed

Chapter 7 IOC ( 14 pages)
Introduction   IOC input    IOC output  IOC data transfer timing  IOC data synchronize
tasks:
1.  control data input from input stage or PCM interface
2.  control data output from output stage or PCM interface
3.  control FIFOs via FIFO controller

ADC0, ADC1, ADC2, ADC3 (18bit only, need to extend to 24bit)
PCM0, PCM1 (normally 24 bit)
D_IOC_FIFO_CFG_reg --> D_IOC_FIFO_CFG_ADCx_SHIFT bit
select FIFO connected to input channel:
D_IOC_INPUT_CFG reg --> IOC_INPUT_CFG_xxx_STORE bit
Dynamic range extension:  IDRX0 (ADC0&ADC1)  IDRX1(ADC2&IDC3)
More than one input source can be saved into the same FIFO:
in time sequence:  ADC0, ADC2, ADC1, and ADC3
                        or: PCM0, PCM1
one 18bit DAC output channel
two pcm:  pcm0 & pcm1
when to get data in, when to send data out, synchronize pcm and adc&dac
General Purpose Timers:  two



Chapter 8 Input Stage (22 pages)

Chapter 9 Output Stage (8 pages)