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Tuesday, October 12, 2010
Sunday, October 10, 2010
Starkey Lab Project (Continued with Oct. 7, 2010)
CFX core
According to 1. encoding format 2. Unit dedicated to, CFX instructions are categorized into several types.
All 32 bit instrucitons. No two-word instructions.
1. Long Instructions: only single instruction in the 32-bit instruction word.
a. control flow b. memory load or store with full-sized address/offset
c. load and store indirect to P memory
d. load full-sized immediate
e. pointer arithmetic with full-sized immeidate
f. system control
2. Arithmetic-Move Instructions: Arithmetic part (DCU) + Move part (DMU or AGUs)
3. Move-Move Instructions: Move part (DMU or AGUs) + Move part (DMU or AGUs)
According to 1. encoding format 2. Unit dedicated to, CFX instructions are categorized into several types.
All 32 bit instrucitons. No two-word instructions.
1. Long Instructions: only single instruction in the 32-bit instruction word.
a. control flow b. memory load or store with full-sized address/offset
c. load and store indirect to P memory
d. load full-sized immediate
e. pointer arithmetic with full-sized immeidate
f. system control
2. Arithmetic-Move Instructions: Arithmetic part (DCU) + Move part (DMU or AGUs)
3. Move-Move Instructions: Move part (DMU or AGUs) + Move part (DMU or AGUs)
Thursday, October 7, 2010
Starkey Lab Project (continued with Oct. 6, 10)
Doc 2, Chapter 4 Hear Core
Microcode Module --> linked up --> Function Chains
System_control_register (D_System_Ctrl): Hear_pause bit, Hear_resume bit, Hear_running bit, Hear_Rest bit
Function_chain_control_reg (D_Hear_FC_Enable)
D_Hear_CMD_0_7 & D_Hear_CMD_8_15
D_Hear_FC_Priority: Normal & High High Priority Funciton chains are handled first
if the same priority level, CFX command first, then FIFO A interrupt, then FIFO B interrupt
24 funcitons trigger accepted: 16 from CFX commands, 8 from FIFO A&B interrupt
D_Hear_FC_Status: pending or not
Blcok_Floating_Point_reg (D_HEAR_BFP):
Chapter 5 Memory (16 pages)
all memories are signle port.
program memory & data memory
memory attached to CFX & memory attached to Hear core
all memory attached to Hear core can be accessed by CFX by P bus or X bus
Write-back-buffers: allow the sytem to read back the value written to the memory address in the previous cycle without stalling the instruction pipeline.
Interrupt Vector:
system-rest, watchdog, timer1, timer2, spi, iic, shared iis and pcm, gpio, hear event 0~7, Fifo A0~3, B0~3,
UART Receive, UART Transmit
Chapter 6 FIFO Controller ( 10 Pages)
FIFO A 0 , 1, 2, 3
FIFO B 0, 1, 2, 3
Each FIFO -- seperate control registers --> map to X memory space --> 24bit
START
END
SIZE
Enable: note: enalbe register is P memory space
FIFO buffers for: block input, block output, application
FIFO_PTR and FIFO_Count
IOBLOCK_PTR and BASE_PTR and BLOCK_SIZE and BLOCK_CNT
FIFO access priority is fixed
Chapter 7 IOC ( 14 pages)
Introduction IOC input IOC output IOC data transfer timing IOC data synchronize
tasks:
1. control data input from input stage or PCM interface
2. control data output from output stage or PCM interface
3. control FIFOs via FIFO controller
ADC0, ADC1, ADC2, ADC3 (18bit only, need to extend to 24bit)
PCM0, PCM1 (normally 24 bit)
D_IOC_FIFO_CFG_reg --> D_IOC_FIFO_CFG_ADCx_SHIFT bit
select FIFO connected to input channel:
D_IOC_INPUT_CFG reg --> IOC_INPUT_CFG_xxx_STORE bit
Dynamic range extension: IDRX0 (ADC0&ADC1) IDRX1(ADC2&IDC3)
More than one input source can be saved into the same FIFO:
in time sequence: ADC0, ADC2, ADC1, and ADC3
or: PCM0, PCM1
one 18bit DAC output channel
two pcm: pcm0 & pcm1
when to get data in, when to send data out, synchronize pcm and adc&dac
General Purpose Timers: two
Chapter 8 Input Stage (22 pages)
Chapter 9 Output Stage (8 pages)
Microcode Module --> linked up --> Function Chains
System_control_register (D_System_Ctrl): Hear_pause bit, Hear_resume bit, Hear_running bit, Hear_Rest bit
Function_chain_control_reg (D_Hear_FC_Enable)
D_Hear_CMD_0_7 & D_Hear_CMD_8_15
D_Hear_FC_Priority: Normal & High High Priority Funciton chains are handled first
if the same priority level, CFX command first, then FIFO A interrupt, then FIFO B interrupt
24 funcitons trigger accepted: 16 from CFX commands, 8 from FIFO A&B interrupt
D_Hear_FC_Status: pending or not
Blcok_Floating_Point_reg (D_HEAR_BFP):
Chapter 5 Memory (16 pages)
all memories are signle port.
program memory & data memory
memory attached to CFX & memory attached to Hear core
all memory attached to Hear core can be accessed by CFX by P bus or X bus
Write-back-buffers: allow the sytem to read back the value written to the memory address in the previous cycle without stalling the instruction pipeline.
Interrupt Vector:
system-rest, watchdog, timer1, timer2, spi, iic, shared iis and pcm, gpio, hear event 0~7, Fifo A0~3, B0~3,
UART Receive, UART Transmit
Chapter 6 FIFO Controller ( 10 Pages)
FIFO A 0 , 1, 2, 3
FIFO B 0, 1, 2, 3
Each FIFO -- seperate control registers --> map to X memory space --> 24bit
START
END
SIZE
Enable: note: enalbe register is P memory space
FIFO buffers for: block input, block output, application
FIFO_PTR and FIFO_Count
IOBLOCK_PTR and BASE_PTR and BLOCK_SIZE and BLOCK_CNT
FIFO access priority is fixed
Chapter 7 IOC ( 14 pages)
Introduction IOC input IOC output IOC data transfer timing IOC data synchronize
tasks:
1. control data input from input stage or PCM interface
2. control data output from output stage or PCM interface
3. control FIFOs via FIFO controller
ADC0, ADC1, ADC2, ADC3 (18bit only, need to extend to 24bit)
PCM0, PCM1 (normally 24 bit)
D_IOC_FIFO_CFG_reg --> D_IOC_FIFO_CFG_ADCx_SHIFT bit
select FIFO connected to input channel:
D_IOC_INPUT_CFG reg --> IOC_INPUT_CFG_xxx_STORE bit
Dynamic range extension: IDRX0 (ADC0&ADC1) IDRX1(ADC2&IDC3)
More than one input source can be saved into the same FIFO:
in time sequence: ADC0, ADC2, ADC1, and ADC3
or: PCM0, PCM1
one 18bit DAC output channel
two pcm: pcm0 & pcm1
when to get data in, when to send data out, synchronize pcm and adc&dac
General Purpose Timers: two
Chapter 8 Input Stage (22 pages)
Chapter 9 Output Stage (8 pages)
Wednesday, October 6, 2010
My post box
Yang Jingbo
Post Box: 44444
Eden Prairie, MN 55344
Where is the post box?
US Post Service: 8725 Columbine Rd, Eden Prairie, MN, 55344
Contact: (952)-944-7186
Note: two keys for the post box, only applied 6 months
Post Box: 44444
Eden Prairie, MN 55344
Where is the post box?
US Post Service: 8725 Columbine Rd, Eden Prairie, MN, 55344
Contact: (952)-944-7186
Note: two keys for the post box, only applied 6 months
Starkey Lab Project ( continued from Oct 3, 10)
Current Project: Denver ( two series: Opal RIC 312 with RF & Power 13 BTE)
New Project: Evanston (two series: Ezairo Only wireless & Ezaino +E2M2)
E2M2 with a V8 uP which is majorly deal with wireless communication with wireless Receiver/Transfer chip.
Doc 2: Hardware Reference (210 pages)
Chapter 1: Introduction (3 pages)
pre-requirement: assembly level programming + dsp application + audio systems + dsp tools.
Chapter 2: System Overview (6 pages)
CFX core: data flow control + dsp applications
Hear core: help CFX to do dsp applications, such as WOLA, FFT etc.
IOC: together with FIFO, provide data input and output to and from CFX core and Hear core.
CPX local memory: Program Memory + X data memory + Y data memory
Hear local memory: Microcode memory
Shared memory: can be accessed by Hear core and CFX core.
Hear core:
Microcode modules --> function chains --> triggered by CFX commands or events from FIFO
Floating point block: for large dynamic range data such as subband
Hear core shared memory: for tempory data, algorithm coefficients, signal data.
FIFO:
1. for circular buffer
2. access conflict from the two cores
3. track data input and output, trigger function chains. etc.
Peripherial:
1. an interrupt controller
2. two general purpose timers
3. a watch-dog timer
4. crc
5. security block
Interfaces:
1. IIC debug interface
2. IIC general purpose interface
3. SPI interface
4. UART interface
5. 5 LSAD inputs
6. 5 GPIO pads
IOC:
1. 4 input channels multiplexed from 5 analog input
2. 1 output channel to drive receiver
IIS and PCM interface:
1. communicate with iis device
2. communicate with pcm device
3. communicate with NOAHlink device
Clock:
1. one on-chip oscillator: 5.12M
2. one standby oscillator
3. allow for selection other clock source
4. series of clock divider
Chapter 3: CFX core (4 pages)
1. Processor Overview
CFX core: dual Harvard, duaol MAC architecture, 24bit
BootROM on it to initialize applications
Debug controller, memory mapped registers
2. Application Overview
Tasks run on CFX core:
Configure IOC and input stage/IIS or PCM to get input
Configure IOC and output stage/IIS or PCM to distribute output signal
Configure FIFO to handle input, output and immediate data
Configure the HEAR core
Execute DSP algorithms
Support Debug
Chapter 4: Hear core (10 pages)
1. Overview
not programmable, no direct debug access,
2. Function Chain Controller
3. Block Floating-Point
New Project: Evanston (two series: Ezairo Only wireless & Ezaino +E2M2)
E2M2 with a V8 uP which is majorly deal with wireless communication with wireless Receiver/Transfer chip.
Doc 2: Hardware Reference (210 pages)
Chapter 1: Introduction (3 pages)
pre-requirement: assembly level programming + dsp application + audio systems + dsp tools.
Chapter 2: System Overview (6 pages)
CFX core: data flow control + dsp applications
Hear core: help CFX to do dsp applications, such as WOLA, FFT etc.
IOC: together with FIFO, provide data input and output to and from CFX core and Hear core.
CPX local memory: Program Memory + X data memory + Y data memory
Hear local memory: Microcode memory
Shared memory: can be accessed by Hear core and CFX core.
Hear core:
Microcode modules --> function chains --> triggered by CFX commands or events from FIFO
Floating point block: for large dynamic range data such as subband
Hear core shared memory: for tempory data, algorithm coefficients, signal data.
FIFO:
1. for circular buffer
2. access conflict from the two cores
3. track data input and output, trigger function chains. etc.
Peripherial:
1. an interrupt controller
2. two general purpose timers
3. a watch-dog timer
4. crc
5. security block
Interfaces:
1. IIC debug interface
2. IIC general purpose interface
3. SPI interface
4. UART interface
5. 5 LSAD inputs
6. 5 GPIO pads
IOC:
1. 4 input channels multiplexed from 5 analog input
2. 1 output channel to drive receiver
IIS and PCM interface:
1. communicate with iis device
2. communicate with pcm device
3. communicate with NOAHlink device
Clock:
1. one on-chip oscillator: 5.12M
2. one standby oscillator
3. allow for selection other clock source
4. series of clock divider
Chapter 3: CFX core (4 pages)
1. Processor Overview
CFX core: dual Harvard, duaol MAC architecture, 24bit
BootROM on it to initialize applications
Debug controller, memory mapped registers
2. Application Overview
Tasks run on CFX core:
Configure IOC and input stage/IIS or PCM to get input
Configure IOC and output stage/IIS or PCM to distribute output signal
Configure FIFO to handle input, output and immediate data
Configure the HEAR core
Execute DSP algorithms
Support Debug
Chapter 4: Hear core (10 pages)
1. Overview
not programmable, no direct debug access,
2. Function Chain Controller
3. Block Floating-Point
Monday, October 4, 2010
Starkey Lab Orientation
1. Perforce System
Ch1: How perforce works (4 pages)
Ch2: Working in perforce (10 pages)
Ch3: Next Steps (2 pages)
Ch1: How perforce works (4 pages)
Ch2: Working in perforce (10 pages)
Ch3: Next Steps (2 pages)
Sunday, October 3, 2010
Starkey Lab Project: Hardware Platform and Programming Intruction
Four major documents at hand:
1. Programming Introduction (78 pages)
2. Hardware Reference (210 pages)
2.1 CPX core (426 pages)
2.2 Hearing Accelerator Core (354 pages)
The system is designed by ON semiconductor, which is built up in 1999.
Doc 1: Programming Introduction
Chapter 1: Introduction Chapter 2 Architecture Overview Chapter 3 Design Information
Chapter 4: Sample code Chapter 5: Porting Guide
Doc 2: Hardware Reference
Chapter 1: Introduction Chapter 2: System Overview Chapter 3: CFX core
Chapter 4: Hear Core Chapter 5: Memory Chapter 6: Fifo controller
Chapter 7: Input/Output Controller Chapter 8: Input stage Chapter 9: Output Stage
Chapter 10: PCM & IIS interface Chapter 11: Peripherials Chapter 12: External Interfaces
Chapter 13: Clock Components Chapter 14: Power Components
Addix: registers, sampling frequency
Doc 2.1 CFX core
Chapter 1: Introduction Chapter 2: CFX architecture overview Chapter 3: Instruction type
Chapter 4: Data Computation Units Chapter 5: Data movement Units Chapter 6: Address Generator
Chapter 7: Program Control Units Chapter 8: Memory spaces Chapter 9: Processing Modes
Chapter 10: CPX instructin Set
Addix: Instruction Set Summary Opcode Map
Doc 2.2 Hear core
Chapter 1: Introduction Chapter 2: Usage Model Chapter 3: Modules
Chapter 4: Moduel Reference Chapter 5: Hear Configuration Tool
Addix: optimized WOLF windows
Now start to go through doc 1, Chapter 1.
Board Name: Ezairo 5900
CFX: 2 MAC 24bit DSP Coare
Hear core
FIFO
130nm technology
CRC generator & security module & RF interface
doc 1, chapter 2 (8 pages)
CFX core:
Task1: configure the system
Task2: coordinate the flow of signal data progressing through the system
Task3: do some signal processing applications that cannot be handled by Hear core.
CFX core features:
1. harvard structure, seperate progrm memory and two data memories with seperate buses.
2. can access to the Hear core memories.
3. Both ROM and RAM for program to store user's applications and interrupt vector. use as instruction memory if through the instruction memory bus. use as data for cfx core if through P memory bus.
4. P bus can be used to access Hear core microcode memory
5. Two sepearate data memories: 24bit X and 24bit Y. or 48bit XY.
6. X bus can also access Hear core memories and registers.
Hear core features:
1. 24bit signal processing engine.
2. FIR/IIR, vector based arithmetic operation, WOLA filterbank, FFT etc.
3. Block Floating Point (BFP): avoid overflow
4. Hear core supports 24 different function chains: 16 from CFX, 8 from interrupt triggered by FIFO controller
Shared Memory:
1. 48 bit width
2. can be accessed by CFX via P bus and X bus.
3. H0, H1, H2, H3,H4, H5: general memory for filter bank etc. 128x48bit
4. A & B for FIFO controller 1024x24bit
5. C & D for microcode modules 1024x24bit
6. Hear can access data 96bit a time for special algorithms.
FIFO controller:
1. for circular buffer
2. resolve access conflict of the two cores via shared memory bus
3. it tracks incoming data and output data. trigger funciton chain of Hear core and interrupt of CFX core.
IO controller:
1. any combination of 4 analog input channels (in input stage) and two pcm channels
2. output to direct digital output or 2 pcm channels.
Firmware components:
1. accessible using ON semiconductor SignaKlara IDE, containing:
a. system included files and macros
b. system library
c. math library
d. eeprom library
e. file system
f. program ROM
g. bootloader
Doc 1, chapter 3(8 pages)
Orela 4500 Ezairo 5900
RCore CFX core
Wola filter Hearing core
load balance on two cores is important to power efficiency.
partition algorithms
fixed size, try to balance noise and power-consuming
data flow:
Orela 4500: input stage --> input fifo --> Rcore --> ouptut fifo --> output stage
Ezairo 5900: much more complex IOC and FIFO Controller, perfect for adptive feedback canceller.
Doc 1, chapter 4 (10 pages)
sample code as template, for learn purpose, not most efficient or optimal way
1. Programming Introduction (78 pages)
2. Hardware Reference (210 pages)
2.1 CPX core (426 pages)
2.2 Hearing Accelerator Core (354 pages)
The system is designed by ON semiconductor, which is built up in 1999.
Doc 1: Programming Introduction
Chapter 1: Introduction Chapter 2 Architecture Overview Chapter 3 Design Information
Chapter 4: Sample code Chapter 5: Porting Guide
Doc 2: Hardware Reference
Chapter 1: Introduction Chapter 2: System Overview Chapter 3: CFX core
Chapter 4: Hear Core Chapter 5: Memory Chapter 6: Fifo controller
Chapter 7: Input/Output Controller Chapter 8: Input stage Chapter 9: Output Stage
Chapter 10: PCM & IIS interface Chapter 11: Peripherials Chapter 12: External Interfaces
Chapter 13: Clock Components Chapter 14: Power Components
Addix: registers, sampling frequency
Doc 2.1 CFX core
Chapter 1: Introduction Chapter 2: CFX architecture overview Chapter 3: Instruction type
Chapter 4: Data Computation Units Chapter 5: Data movement Units Chapter 6: Address Generator
Chapter 7: Program Control Units Chapter 8: Memory spaces Chapter 9: Processing Modes
Chapter 10: CPX instructin Set
Addix: Instruction Set Summary Opcode Map
Doc 2.2 Hear core
Chapter 1: Introduction Chapter 2: Usage Model Chapter 3: Modules
Chapter 4: Moduel Reference Chapter 5: Hear Configuration Tool
Addix: optimized WOLF windows
Now start to go through doc 1, Chapter 1.
Board Name: Ezairo 5900
CFX: 2 MAC 24bit DSP Coare
Hear core
FIFO
130nm technology
CRC generator & security module & RF interface
doc 1, chapter 2 (8 pages)
CFX core:
Task1: configure the system
Task2: coordinate the flow of signal data progressing through the system
Task3: do some signal processing applications that cannot be handled by Hear core.
CFX core features:
1. harvard structure, seperate progrm memory and two data memories with seperate buses.
2. can access to the Hear core memories.
3. Both ROM and RAM for program to store user's applications and interrupt vector. use as instruction memory if through the instruction memory bus. use as data for cfx core if through P memory bus.
4. P bus can be used to access Hear core microcode memory
5. Two sepearate data memories: 24bit X and 24bit Y. or 48bit XY.
6. X bus can also access Hear core memories and registers.
Hear core features:
1. 24bit signal processing engine.
2. FIR/IIR, vector based arithmetic operation, WOLA filterbank, FFT etc.
3. Block Floating Point (BFP): avoid overflow
4. Hear core supports 24 different function chains: 16 from CFX, 8 from interrupt triggered by FIFO controller
Shared Memory:
1. 48 bit width
2. can be accessed by CFX via P bus and X bus.
3. H0, H1, H2, H3,H4, H5: general memory for filter bank etc. 128x48bit
4. A & B for FIFO controller 1024x24bit
5. C & D for microcode modules 1024x24bit
6. Hear can access data 96bit a time for special algorithms.
FIFO controller:
1. for circular buffer
2. resolve access conflict of the two cores via shared memory bus
3. it tracks incoming data and output data. trigger funciton chain of Hear core and interrupt of CFX core.
IO controller:
1. any combination of 4 analog input channels (in input stage) and two pcm channels
2. output to direct digital output or 2 pcm channels.
Firmware components:
1. accessible using ON semiconductor SignaKlara IDE, containing:
a. system included files and macros
b. system library
c. math library
d. eeprom library
e. file system
f. program ROM
g. bootloader
Doc 1, chapter 3(8 pages)
Orela 4500 Ezairo 5900
RCore CFX core
Wola filter Hearing core
load balance on two cores is important to power efficiency.
partition algorithms
fixed size, try to balance noise and power-consuming
data flow:
Orela 4500: input stage --> input fifo --> Rcore --> ouptut fifo --> output stage
Ezairo 5900: much more complex IOC and FIFO Controller, perfect for adptive feedback canceller.
Doc 1, chapter 4 (10 pages)
sample code as template, for learn purpose, not most efficient or optimal way
Saturday, October 2, 2010
Sucess depends on DETAILS (无他,认真二字而已)
成功之路: 欲望 --> 计划 --> 行动 --> 坚持 --> 成功
计划要注意细节, 行动后要分析结果, 反省不好的地方,尤其是细节的地方
计划要注意细节, 行动后要分析结果, 反省不好的地方,尤其是细节的地方
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